Semiconductors & Hi-Tech
Representative engagementCatching wafer defects earlier with computer vision
A visual inspection pipeline that prioritizes defect patterns and gives yield engineers the process context behind every flag.
Context
The situation
A semiconductor manufacturer inspects wafers with optical tools that flag anomalies using fixed rules. Engineers review large volumes of flagged images, most of which are not real defects, while subtle systematic patterns are found only after lots have moved downstream.
Problem definition
How we framed it
The problem was not detection alone but prioritization: which flagged images deserve an engineer's attention, which patterns indicate a process excursion and how to route each case to the right team with context. We defined success with the yield engineering team as fewer false alarms reaching engineers and earlier identification of systematic patterns, measured on historical lots.
Delivery
What we built
- An ingestion pipeline for inspection images and wafer maps with lot, tool and process context
- Defect classification and wafer map pattern recognition models trained on labeled history with active learning for new patterns
- A review interface where engineers confirm, correct and annotate, feeding the next training cycle
- Routing rules that send cases to process, equipment or test teams with the evidence attached
- Monitoring for model drift as processes and products change, with retraining pipelines
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Operating impact
What changes for the business
Engineers spend their time on the images that matter, systematic patterns surface while corrective action is still possible, and the organization builds a labeled history that keeps improving the system. The approach generalizes to other inspection steps and to test data correlation.
Related services
Services involved
Next step
Ready when you are.
Tell us what you are trying to build and we will come back with a point of view, not a pitch.